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All Silicon IP


This IP supports operational data rates 80Mbps to 1.5Gbps per One lane for HS mode, and up to 10Mbps for LP modes transfer rates.

Block Diagram


  • MIPI D-PHY version 1.2 compliant PHY receiver
  • Consists of 4 data lane and 1 clock lane
  • Supports HS mode (80Mbps to 1.5Gbps) and LS mode (up to 10Mbps)
  • Integrated control interface logic to supports PHY Protocol Interface (PPI)
  • Integrated 100-ohm termination resistors with common-mode biasing
  • Configurable analog characteristics
    • Timing skew
    • Terminator resistance
    • BGR voltage
  • 1.2V power supply
  • Support GlobalFoundry 55nm LPe process

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