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All Silicon IP

Overview

SLI PSDUHS2A_PHY is PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface for both SDHC and SDXC. SLI s UHS-II PHY IP is most successful and sophisticated in the market. SLI has licensed 11products and 9 products are in mass production. By using SLI s unique SerDes technology, SLIPSDUHS2A_PHY achieves 312MB/s that is the maximum speed for UHS-II with the low power consumption. This PHY IP can be applied to both the device and host sides including SDIO and hence it can be utilized for SOCs for various applications including SD cards, digital cameras, digital videos, digital TVs, media players and personal computers.

Tech Specs

FoundryGlobalFoundries
Geometry nm28
Target Process NodeSLP

Features

  • SD UHS-II compliant Physical layer for device
  • Optimized for UHS-II Host
  • Supports both Full Duplex mode and Half Duplex mode
  • Power Dormant Mode
  • 1.8V/1.0V power supply
  • Configurable analog characteristics
    • Driver swing voltage
    • Driver rise time / fall time
    • BGR voltage
    • PLL loop filter
    • PLL VCO gain and offset-frequency
    • PLL lock detector accuracy
    • Regulator voltage
    • DET threshold voltage
  • Built in self test
  • Various loopback modes
  • Supports metal option 6U1x_2T8x_LB and up (Two 8x metals required)
  • Used devices
    • Core voltage RVT-NMOS/PMOS, LVT-NMOS/PMOS, Diode
    • 1.8V NMOS/PMOS, Diode, NMOS cap, BJT
    • Un-silicided poly resister
    • No DNW required
  • PHY area : 1.05mm x 1.0mm = 1.05m2 (including IO)
  • Compliant SD4 ESD requirements, 4kV(HBM) 200V(MM)

Deliverables

Datasheet Integration guideline GDSII or Phantom GDSII Layer map table CDL netlist for LVS LEF Verilog behavior model Liberty timing model DRC/LVS/ERC results

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