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All Silicon IP

Overview

SLIPSDUHS3A_PHY is PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface for both full size SDHC and SDXC. By using SLI s unique SerDes technology, SLIPSDUHS2A_PHY achieves 624MB/s that is the maximum speed for UHS-III with the low power consumption. This PHY IP can be applied to both the device and host sides including SDIO and hence it can be utilized for SOCs for various applications including SD cards, digital cameras, digital videos, digital TVs, media players and personal computers.

Block Diagram

Features

  • SD UHS-II Gen.2 compliant Physical layer
  • Configurable for Host or Device
  • Supports both Full Duplex mode and Half Duplex mode
  • Dormant mode
  • 1.8V/1.2V power supply
  • Configurable analog characteristics
    • Transmitter swing voltage
    • Transmitter rise time / fall time
    • Transmitter common mode voltage
    • Transmitter de-emphasis strength
    • Receiver equalizer strength
    • BGR voltage
    • PLL loop filter
    • PLL VCO gain and offset-frequency
    • Regulator voltage
    • DET threshold voltage
  • Built in self test
  • Loopback modes
  • Supports metal option 1P6M1T and up.
  • Compliant SD6 ESD requirements, 4kV(HBM) 200V(MM)
  • 500V CDM ESD and 100mA latch-up tolerance

Deliverables

Datasheet Integration guideline GDSII or Phantom GDSII Layer map table CDL netlist for LVS LEF Verilog behavior model Liberty timing model DRC/LVS/ERC results

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