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Overview

The Cadence® Tensilica® Vision digital signal processor (DSP) family is designed for demanding imaging, computer vision, and neural network (NN) applications in the mobile, automotive, surveillance, gaming, drone, and wearable markets. The Vision P5 DSP and the Vision P6 DSP are our two imaging- and computer vision-specific products that establish a new standard in high-performance, low-energy digital signal processing. With addition of the Vision C5 DSP, we now have a member designed specifically for NN processing. Plus, since all our DSPs are built on the highly successful Cadence Tensilica Xtensa® processor, the Vision DSP family shares the same development environment. For sufficient pixel processing throughput, the Vision DSP family architecture incorporates advanced VLIW/SIMD support for the industry's highest number of ALU and MAC operations per processor cycle, as well as the industry's widest and most flexible memory bus. Specialized instructions also allow the Vision DSP family to efficiently speed up pixel processing. In our Vision C5 DSP, we have given significant focus on optimized implementation of all the layers of a NN rather than just the convolution layer. These instructions were optimized in close collaboration with a number of customers and partner companies and after detailed profiling of key imaging, vision, and NN applications. Various architecture enhancements boost the performance while keeping the energy consumption low. The Vision DSP family provides unprecedented flexibility in system implementations at power-consumption levels that significantly reduce the need for hardware accelerators. The DSPs also offer an integrated DMA engine, interface for instruction memory, instruction cache, and two AXI interfaces. It offers industry's widest data memory bus of 1024-bit. In the Vision P5 and P6 DSPs, we also offer an optional vector floating-point unit.

Benefits

  • Provides a high-performance, energy-efficient imaging, vision, and NN embedded DSP
  • Implements 64-way 8-bit SIMD on Vision P DSPs and 128-way 8-bit SIMD on Vision C DSPs with multiple VLIW slots
  • Achieves up to 1.1GHz on 16nm process technology
  • Only DSPs in the industry to offer 1024-bit memory bus for transferring the high-resolution data associated with today?s imaging systems
  • Provides a complete subsystem using the integrated DMA that allows the system to transfer high-resolution data directly into the local memory of the DSP, thus hiding the data access latency associated with accessing data from an external DRAM
  • Implements the Tensilica SuperGather? enhanced memory interface on Vision P DSPs to quickly and efficiently read/write non-contiguous locations from local memory
  • Features an instruction set that?s customized for better code density, fewer cycles, and lower power
  • Provides a comprehensive software tool suite for quickly implementing high-performance imaging pipelines in C
  • Features instruction-set extensibility for more algorithm-specific optimization via Tensilica Instruction Extensions (TIE)
  • The Vision P DSPs deliver scalable, optimized performance with low energy for computer-vision and pixel-processing applications that span a large range of data types from 8b to 32b, such as face detection, object detection, lens distortion correction, and many more advanced vision applications
  • The Vision C DSP delivers a efficient, flexible, scalable, and future-proof solution for the NN problem
  • Optional vector floating-point unit (VFPU) in the Vision P DSPs offers flexibility to provide high-precision math at a minimal area penalty

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