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Continuing the highly successful line of DisplayPort link controller cores, the Trilinear VF-111T DisplayPort Transmitter core has been updated to include full support for the Video Electronic Standards Association (VESA) DisplayPort 1.4 standard. The core is available for implementation in FPGA or ASIC devices utilizing a variety of physical layer (PHY) interfaces available through third party partners. The transmitter is currently implemented for evaluation in multiple FPGA platforms.

The fifth generation of Trilinear DisplayPort link controllers provide significantly improved functionality including enhanced support for the complete DisplayPort 1.4 including Display Stream Compression (DSC), Forward Error Correction (FEC), embedded DisplayPort 1.4a with Panel Self-Refresh2 as well as enhanced audio functionality. As with previous generations of the cores, Multi-Stream Transport and HDCP 1.3 and 2.2 are fully supported. The link controllers support a wide range of implementations from simple to complex using a highly configurable architecture for an optimal balance of features and area. The core hasbeen tested for DisplayPort compliance and compatibility and is available for licensing now. The IP is already proven in silicon and licensed by lead partners.

The Trilinear DisplayPort 1.4 link controller has been designed to provide full featured integration into both FPGA and ASIC target environments with no loss of performance. This allows for ASIC prototyping as well as deployment of production quality solutions in FPGA. The industry standard AMBA APB-4 host interface allows for easy integration into either existing or new designs.

Block Diagram


  • Overview
    • DisplayPort 1.4 support including HBR2 and MST.
    • Embedded DisplayPort 1.4
    • Multiple process PHY support including 28nm, 40nm, and 65nm.
    • Link policy maker SW included
  • Interfaces
    • Standard VS/HS video interface
    • 1, 2 or 4 pixels per input cycle
    • 135MHz / 81MHz or 108MHz reference clock
    • AMBA APB-4 Slave Interface
  • Core Details
    • Multiple link rate support up to 8.1 Gbps across 1,2, or 4 lanes
    • Optional secondary channel support
    • Optional HDCP 1.3 or HDCP 2.2 support
    • Optional eDP 1.3 support
    • Deep color support
  • Reference Software
    • DisplayPort 1.4 compliant link policy maker
    • 'C' source code included
    • Fully documented API
  • FPGA Development Platform
    • 32-bit MCU based system
    • Real time video input
    • Includes the VF-111T Link Controller, DDR-3 system and display controller


  • HDL source files for the function design
  • HDL source files for block level and top level testing
  • Functional specification
  • Timing constraints summary document
  • Generic SRAM simulation models
  • C Reference Driver
  • C Link Policy Maker

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