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Overview

This ultra-low power, processing-efficient system enables OEMs to extend battery life while designing in sophisticated, always-on sensing capabilities on mobile devices. Advanced sensor algorithms such as voice triggering, motion compensated heart rate monitoring, and indoor navigation can be achieved at significant power reduction compared to competing MCU-based solutions. Unlike traditional MCU-based solutions, the EOS S3 is a multi-core, sensor processing system that enables sophisticated algorithm partitioning to facilitate the lowest possible power consumption for the designated task. The EOS S3 employs not only fundamental, but also very sophisticated, always-on, context-aware sensing capabilities while staying well within the strict power budgets of smartphone, wearable, and IoT designs.

Benefits

  • Ultra-Low Power Operation The lowest power sensor processing system on the market, the EOS S3 is capable of running fundamental algorithms as well as the most computational-intensive algorithms on the market today, with extra capacity in anticipation of future software requirements.
  • Computational Efficiency The EOS S3 employs QuickLogic s proprietary Flexible Fusion Engine (FFE), an ARM Cortex M4-F MCU, and programmable logic with partitioning capability to provide the most efficient processing capability for the task at hand. Routine and less computationally intensive algorithms can be handled in the FFE with a powered-down M4-F.
  • Flexibility Reprogrammable fabric provides the capability to incorporate and modify customer application-specific logic on the fly, as often as required.
  • Optimized Voice Processing By integrating dedicated logic for Sensory s Low Power Sound Detector, and support for I S and PDM digital microphones, the EOS S3 platform has been optimized for always-on, always-listening voice recognition applications at the absolute lowest power. In fact, the total average power for voice recognition - including the power of a digital microphone - is less than 1 mA - as measured at the battery.
  • Comprehensive Integrated Solution QuickLogic offers a full suite of sensor fusion algorithms for incorporation with the EOS S3 system. Customers can also employ their own or 3rd-party algorithms with our advanced Integrated Development Environment (IDE).

Block Diagram

Features

  • 32 kHz Oscillator with Real-Time Clock (RTC)
    • 32 kHz crystal oscillator (external crystal required) with bypass option
    • 1 Hz clock generation with compensation register
    • RTC function with one alarm register
    • Start time of 350uS
  • High Frequency Clock Source
    • Programmable frequency (2 MHz to 80 MHz)
    • Calibrated output (using 32 kHz input)
    • Startup time of 410 µs
    • Clock divider can be programmed in 12 bits
  • Power Management Unit
    • Low-power mode with fast wake-up
    • Programmable power modes (deep sleep, sleep with retention, and active)
    • Multiple power domains
    • Power sequencing for sleep and wake-up entry and exit
    • Wake-up triggers via internal and external events
    • Internal LDO support
  • M4-F Subsystem
    • Cortex M4-F controller with floating point unit (M4-F)
    • Embedded SRAM (up to 512 KB) for code and data memory
    • Vectored interrupt support
    • Wakeup interrupt controller
    • 2-pin SWD port
  • FFE
    • 50 KB control memory
    • 16 KB data memory
    • Single cycle MAC
  • Packet FIFOs Batching Memory
    • Multiple packet FIFOs to support the FFE to application
    • processor/M4-F data transfers:
      • 8 KB packet FIFO with ring-buffer mode support
      • 256 x 32 packet FIFO and two 128 x 32 packet FIFOs
    • 128 KB of M4-F SRAM can be used as HiFi sensor batching memory
  • System DMA
    • 16 channels of DMA allows efficient data movement between processing elements
  • SPI Slave
    • SPI slave application processor communication of up to 20 MHz
  • Time Stamping
    • Automatic hardware time stamp on every sensor read in the interrupt mode
    • Up to eight sensor interrupt captured time-stamps (8-bit)
    • Main time stamp of 24-bits
    • Resolution of 1 msec
  • I² C Master and Configurable I² C/SPI Interface
    • I² C master and SPI master with programmable clock pre-scaler
    • Option to disable multi-master support and slave-inserted wait for shorter SCL cycles
    • Configurable for two I² C Masters or one I² C Master and one SPI Master
  • Other Interfaces
    • SPI master for interfacing with serial flash memories and other external SPI-based peripherals of up to 20 MHz
  • Digital Microphone Support
    • I²S microphone
    • PDM microphone
    • Integrated LPSD
  • UART
    • Serial support for M4-F debug and code development
    • Communication with UART-based external peripherals
  • Other Peripherals
    • Timers
    • Watchdogs
    • GPIO controllers
  • ADC
    • Low sampling rate SD 12-bit
  • LDOs
    • On-chip LDO for system logic
    • Separate on-board LDO for memory
  • Programmable Fabric
    • 2-pin SWD port for access to the following memory mapped resources:
      • M4-F internal registers and memories
      • FFE and Sensor Manager memories
      • FFE control registers
      • Programmable fabric memories
      • Programmable fabric designs through generic AHB bus
      • All memory map peripherals such as timers, WDT, SPI master, etc.
      • I²C master used for I2C sensor debug
      • Multiplexed dedicated parallel debug interface
  • Packaging Options
    • 42-ball WLCSP (2.7 mm x 2.4 mm x 0.7 mm) (28 user I/O, 2 VCCIO banks)
    • 64-ball BGA (3.5 mm x 3.5 mm x 0.8 mm) (46 user I/O, 2 VCCIO banks)

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