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All Silicon IP

Overview

MIPI D-PHY version 1.2 compliant PHY receiver (SLIPMPRDPHG55LE) and MIPI D-PHY version 1.2 compliant PHY transmitter (SLIPMPTDCMG55LE)

Applications

Operating conditions for SLIPMPRDPHG55LE and SLIPMPTDCMG55LE
  • Supply voltage for logic: Min. 1.8V, Max. 1.32V
  • Supply voltage for analog:
    • Min. 1.08V, Max. 1.32V for RX
    • Min. 2.25V, Max. 2.75V for TX
  • Junction temperature: Min. -40 °C, Max. 125°C
  • Block Diagram

    Tech Specs

    Target Process NodeGlobalFoundries 55 LPe

    Features

    SLIPMPRDPHG55LE MIPI DPHY Receiver IP on GF55LPe
  • MIPI D-PHY version 1.2 compliant PHY receiver
  • Consists of 4 data lane and 1 clock lane
  • Supports HS mode (80Mbps to 1.5Gbps) and LS mode (up to 10Mbps)
  • Integrated control interface logic to supports PHY Protocol Interface (PPI)
  • Integrated 100-ohm termination resistors with common-mode biasing
    • Configurable analog characteristics Timing skew
    • Terminator resistance
    • BGR voltage
  • 1.2V power supply
  • Support GlobalFoundry 55nm LPe process SLIPMPTDCMG55LE MIPI DPHY & LVDS Transmit Combo IP on GF55LPe
  • MIPI D-PHY version 1.2 compliant PHY transmitter
  • OpenLDI version 0.9 compliant LVDS transmitter
  • Consists of 6 lanes configurable to be 4+1 MIPI and 7 lanes LVDS
  • Supports HS mode (80Mbps to 1.5Gbps) and LS mode (up to 10Mbps) for MIPI mode
  • Support up to 1.5Gbps LVDS with 7:1 serializer
  • Integrated control interface logic to supports PHY Protocol Interface (PPI)
  • Configurable analog characteristics
    • Differential voltage
    • Common mode voltage
    • PLL divider/loop filter
  • Support at-speed loopback BIST
  • 2.5V/1.2V power supply
  • Support GlobalFoundry 55nm LPe process
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