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All Silicon IP

Overview

VISENGI’s Advanced Encryption Standard (AES) IP core provides AES-128, AES-192, and AES-256 encryption and decryption, as per FIPS-197, with a shockingly small resource usage, while allowing a large operating frequency.

Benefits

For user-connection’s convenience this IP core is designed with 32 bits wide buses. Hence, the AES’ native blocks of 128 bits are input as 4 words of 32 bits one after the other, without pauses in between. The same is expected for the keys of size 128 bits (4 contiguous words of 32 bits), 192 bits (6 words), and 256 bits (8 words).

Features

  • AES algorithm following Federal Information Processing Standards 197 (FIPS PUB 197).
  • Constant encryption/decryption throughput, depending only on key size:
    • AES128 (128 bits key): 77 cycles per 128 bits of data (1.66 Mbps/MHz)
    • AES192 (192 bits key): 91 cycles per 128 bits of data (1.40 Mbps/MHz)
    • AES256 (256 bits key): 105 cycles per 128 bits of data (1.21 Mbps/MHz)
  • Low latency one-time key expansion (<100 cycles) on all modes’ start-up.
  • ECB block cipher mode of operation, quick adaptability to any mode (CBC, CTR, ??
  • Extremely simple FIFO-like 32 bits wide I/O.
  • Automatic key-length (AES128/AES192/AES256) inference. The data interfaces used are simple FIFO-like with minimal control bits. The key size (AES128/192/256) is automatically inferred from the number of 32 bits words input when a new key is supplied (4, 6, or 8 cycles). The input/output interfaces of the AES IP core are divided in three different parts:
  • Control Interface: control bit to indicate encryption or decryption.
  • Input Interface: shared 32 bits bus for both supplying a key and user data to encrypt/decrypt. It is a simple FIFO interface with a ready output and a data valid input.
  • Output Interface: simple 32 bits sequential output of the encrypted/decrypted data.
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