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All Silicon IP

Overview

The Alma Technologies AES-P IP Core implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key. The Block Cipher mode of operation is run-time programmable to ECB, CBC, CFB, OFB, or CTR. The AES-P core is available in two variations, the standard AES32-P and the fast AES128-P.

AES32-P has a 32-bit internal datapath, while the AES128-P uses 128-bit datapath. The AES32-P is more compact in size, but offers a lower throughput than the AES128-P. The AES32-P needs 44/52/60 clock cycles to encrypt or decrypt an input block using 128/192/256-bit cipher-key, respectively, while only 11/13/15 clock cycles are required for the same by the AES128-P core.

Block Diagram

Tech Specs

Maturity Available

Features

  • Fully compliant to the Advanced Encryption Standard (AES) (FIPS PUB 197)
  • Run-time programmable encrypt or decrypt
  • Run-time programmable Block Cipher mode: ECB, CBC, CFB, OFB, CTR
  • Run-time programmable cipher-key size: 128-, 192-, 256-bit
  • Includes Round Key Table for storage of Round Key values
  • Optional Key Expansion module for automatic generation of the Round Key values
  • AES32-P: Processes each 128-bit block in 44/52/60 clock cycles for 128/192/256-bit cipher-key respectively
  • AES128-P: Processes each 128-bit block in 11/13/15 clock cycles for 128/192/256-bit cipher-key respectively
  • High-speed, flow controllable, streaming I/O data interfaces
  • Trouble-Free Technology Map and Implementations

Deliverables

  • Clear text VHDL or Verilog RTL source for ASIC designs, or pre-synthesized and verified Netlist for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices
  • Release Notes, Design Specification and Integration Manual documents
  • Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
  • Self checking testbench environment, including sample BAM generated test cases
  • Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

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