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The ES1002 hash core fully implements the SHA-1 (Secure Hash Algorithm RFC 3174). The core can be used for data authentication in digital broadband, wireless or multimedia system. The SHA-1 core processes the input message in 512-bit blocks and produce message digest of 160-bit (for SHA-1). The output data is referred to as a digital signature or quot;fingerprint or message digest of input messages.

Block Diagram


  • Supports SHA-1 Secure Hash Algorithm described in RFC 3174.
  • High speed operation. One clock per hash step. Full SHA-1 is computed in 81 cycles.
  • Supports message padding
  • Allows Time Division Multiplexing (TDM) of several data streams.
  • Simple external interface
  • Simple 32 bit I/O interface
  • Outputs message digest from every input block of data (512-bit block size)
  • Supports user input initialization vectors.
  • Minimal gate count.
  • Support 1.6 Gb/s of data rate for SHA-1 at 250 MHz.
  • Available in ASIC and FPGA Technologies.

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