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Overview

  • Best in its class per-MHz performance
  • Andes Custom Extension™ (ACE) for significant performance efficiency boost
  • Small footprint with low gate count and high code density
  • Speed-up and power reduction for Flash accesses by FlashFetch technology

The new Andes Technology E8 CPU processor core targets Internet of Things (IoT) applications with the unique Andes Custom Extension (ACE) on a power-efficient compact embedded controller. SoC designs for IoT devices demand low power consumption in combination with high performance to handle compute intensive functions such as processing sensor data and wireless protocol stacks. The E8’s unique ACE environment enables designers to specify the architectural element that makes the core ideal for IoT applications. With Andes Custom-OPtimized Instruction deveLOpment Tools (COPILOT), designers can create custom instructions that differentiate their design from competitive offerings, which are based on standard instruction set processors. By adding special instructions, not easily discoverable by hackers, ACE also provides stronger security to a design.

Another E8 feature, FlashFetch, boosts performance while saving power. FlashFetch consists of a small amount of buffer near the processor core that enables repetitive functions to be executed efficiently thus eliminating power consuming flash memory accesses. With a three-stage pipeline, the E8 can achieve 1.82 DMIPS per MHz, which is far higher performance than other 32-bit alternatives while the power consumption and gate-count are as low as 8-bit controllers.

Benefits

AndeStar™V3m Architecture
  • Better performance for modern compiler
  • Smaller die size and lower power consumption
  • Smaller code size
  • Faster SW development and easier maintenance
  • More performance
  • Quick identification of interrupt sources and fast assignment of service routines
  • Performance boost with customized instructions
  • Reduced core size with optimum memory support
  • Friendliness to programmers and compilers

CPU Core

  • Superior performance-per-MHz
  • Superior performance-efficiency, while allowing for high speeds
  • Better performance for branches
  • Speed up procedure returns
  • Application specific configurations
    • More performance
    • Smaller size
  • Stack size determination and runtime overflow error detection
  • Simplification SoC design and debugging
  • Program code performance tuning
  • Slow flash memory acceleration and power consumption reduction
  • Productive: improve SoC s performance, speed, power, and cost with instruction customization
  • Flexible: program the custom instructions as needed
  • Secure: stop reverse engineering in program code by proprietary custom instructions
  • Lower power
  • Simplified SoC integration
  • Faster context switch for real-time applications
  • Better performance-efficiency and low latency
  • Peak power consumption reduction

Memory Subsystems

  • Higher efficiency for program execution
    • Flexible size selection to fit diversified needs
    • Capable of replacing DLM and bus for lower cost
    • Capable of replacing bus for lower cost
  • User-selectable bus interface for optimal efficiency

Applications

  • Connectivity device
  • Sensor hub
  • Wearable device
  • Smart meter
  • Storage device
  • Touch screen controller
  • Battery management
  • Sensor-less motor driver

Block Diagram

Features

AndeStar V3m Architecture
  • 21st-century RISC-like instruction set
  • V3 subset for MCU most frequency used instructions
  • 16/32-bit mixable opcode format
  • All-C Embedded Programming
  • Hardware divider
  • Direct support of up to 32 interrupts with programmable priority levels
  • Andes Custom Extension (ACE)
  • 16MB address space
  • Memory mapped IO

CPU Core

  • 1.82 DMIPS/MHz*
    3.54 CoreMark/MHz*(* Toolchain BSP v 4.1.0)
  • 3-stage pipeline
  • Branch predication
  • Return address stack
  • Choice of multipliers
    • Fast (1 cycle) for performance
    • Small (<0.5K gates) for size
  • Hardware stack protection
  • Processor state bus
  • Performance monitors
  • Interface to FlashFetch IP (separately licensable) which contains following options
    • Prefetching functionality
    • Caching functionality
    • SPI interface to external flash
  • Andes Custom Extension ACE)
    • Simple and flexible interface
    • 1 cycle or multi-cycle instruction latency
    • Up to 3R/2W general-purpose register accesses
    • Logic sharing among custom instructions
    • Support user-defined error status
    • Support instruction interruption
    • Memory accesses through E8
    • ACE Registers (ACR) for more powerful instructions
  • Extensive clock gating and logic gating
  • N:1 core/bus clock ratios
  • Low-latency vectored interrupt
  • Completion of most operations in 1 cycle Single-cycle capable for Local Memory and AHB bus accesses
  • PowerBrake technology

Memory Subsystems

  • Optional External Instruction and Data Local Memory
    • Size: 0KB to 4MB
    • ILM: program code, data and IO
    • DLM: program data and IO
  • BIU supports AHB-lite or APB

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