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Overview

  • Optimized pipeline for best performance with over 1 GHz
  • Dynamic branch prediction accelerates loop execution
  • Unified Local Memory (ULM) for simultaneous accesses
  • 64-bit AXI bus for high bandwidth and low latency
  • MMU and MPU for Linux and RTOS
  • Support for FPU coprocessor and L2 cache

The Andes Technology N13 processor is a high performance CPU core architected for computation intensive applications running either on operating systems or as bare metal. The N13 is designed to serve the demanding requirements of application processors in SoCs for consumer electronics such as HDTVs, home media servers, cable and over-the-top set top boxes, as well as SoCs for the switches and routers delivering content to these devices.

Complete with Memory Management Unit, L1/L2 cache, Local Memory, DMA, FPU, Vectored Interrupt, and Branch Prediction, the N13 easily runs complex operating system such as Linux. And with an 8-stage pipeline and a clock rate over 1 GHz, the core delivers impressive performance of 2.05 DMIPS/MHz to serve the most demanding computing environments. Furthermore, the N13 AndesCore™ supports the latest AndeStar™ architecture, which is accompanied with toolchain, IDE, RTOS, Linux, middleware, and platform development IP. The N13 s strength plus its ecosystem provide designers with the competitive edge for success in their embedded system solutions.

Benefits

AndeStar™ V3 Architecture
  • Better performance for modern compiler
  • Smaller code size
  • Efficient voice applications
  • Better code size and performance
  • Faster SW development and easier maintenance
  • Efficiency and protection with a dedicated kernel stack pointer
  • More performance
  • Better program code size and performance
  • Quick identification of interrupt sources and fast assignment of service routines
  • Full range address space
  • Friendliness to programmers and compilers

CPU Core

  • Superior performance-per-MHz
  • High speed and high performance
  • Better performance for branches
  • Stack size determination and runtime overflow error detection
  • Simplification SoC design and debugging
  • Program code performance tuning
  • Basic read/write/execute memory protection with minimum cost
  • Lower power
  • Simplified SoC integration
  • Faster context switch for real-time applications
  • High bandwidth with lower latency
  • Non-bus locking mechanism
  • For Andes FPU and other customer designed coprocessor unit

Memory Subsystems

  • Higher performance for large program size
    • Accelerating accesses to slow memories
    • Flexible cache configurations
    • VIPT for low power on context switch
  • Higher efficiency for program execution
    • Flexible size selection to fit diversified needs
  • Flexible placement of code and data with minimal latency
  • Efficient data transfer
  • Code & data integrity protection
  • User-selectable bus interface for optimal efficiency

Debug Support

  • Low-cost 2 wire support and industry-standard 5-wire support
  • Flexible configurations to trade off gate count and debugging capabilities
  • Code and data protection by allowing only authorized debugging

Applications

  • Networking device
  • WiFi device
  • GPON
  • Surveillance system
  • ADAS
  • Storage device
  • Digital TV/Set top box
  • Media center

Block Diagram

Features

AndeStar V3 Architecture
  • 21st-century RISC-like instruction set
  • 16/32-bit mixable opcode format
  • Optional saturation instructions
  • 32 general-purpose registers
  • All-C Embedded Programming
  • Shadow stack pointer
  • Hardware divider
  • Aligned and unaligned load/store multiple word instructions
  • Direct support of up to 32 interrupts with programmable priority levels
  • 4G address space
  • Memory mapped IO

CPU Core

  • 2.05 DMIPS/MHz*
  • 3.16 CoreMark/MHz* (* Toolchain BSP v 4.1.0)
  • 8-stage pipeline
  • Extensive branch predication (BTB and RAS)
  • Hardware stack protection
  • Processor state bus
  • Performance monitors
  • Memory Management Unit
    • 32/64/128-entry 4-way set-associative main TLB
    • Extensive clock gating and logic gating
    • Optional hardware page table walker
    • Extensive clock gating and logic gating
    • Support two groups of page size (4KB & 1MB, 8KB & 1MB)
  • Memory Protection Unit
    • 8 memory protection regions
  • Extensive clock gating and logic gating
  • N:1 core/bus clock ratios
  • Low-latency vectored interrupt
  • Coprocessor interface

Memory Subsystems

  • I & D Cache
    • Virtually Indexed and Physically Tagged (VIPT)
    • Size:8KB to 64KB, line size:16B/32B
    • Set associativity: Direct-mapped/ 2 Way
  • Optional External Instruction and Data Local Memory
  • Optional unified local memory interface
  • Optional 2D local memory DMA
  • Error Correcting Code (ECC) for caches and local memory
  • BIU supports 32-bit AHB/2AHB/AHB-lite/APB/AXI
Debug Support
  • 2-wire Serial Debug Port or 5-wire JTAG Debug Port
  • Embedded Debug Module (EDM)
    • Up to 8 breakpoints and watchpoints
    • Secured debug access to system address space

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