www.design-reuse-embedded.com
You are here : design-reuse-embedded.com  > Multi Media Vision  > Audio Video
Download Datasheet        Request More Info
All Silicon IP

Overview

The CAMFE Core implements a flexible, resource-efficient camera front-end processor that receives raw pixel data from a CMOS or CCD sensor and outputs a video stream ready for display, further processing, or compression. The core first converts the Bayer pattern output from the sensor to an RGB image using an efficient de-mosaicing interpolation filter. The interpolated RGB samples are input to the White Balancing stage, which adjusts color intensities so they are appropriate for reproduction in a display. Under its full configuration, the core subsequently proceeds with further steps essential for optimizing the visual quality of the image, running RGB to YUV color space conversion, then performing Contrast Stretching (also called Normalization) and Gamma Correction, and finally applying a Sharpening Filter. The CAMFE Core requires only a few lines of buffering and adds minimal processing latency. It features extremely low power consumption due to the absence of a power-consuming frame buffer and the core s small silicon footprint (less than 15,000 gates). Furthermore, a fine-pipelined structure allows CAMFE to operate at high clock frequencies, and it can process over 150 Mpixels/sec even in low-end FPGAs. The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

Features

CMOS or CCD sensor interface, delivering quality-optimized RGB or YUV images ready for display, compression or further processing Processing Pipeline
  • Bayer Interpolation/De-mosaicing
  • RGB to YUV Conversion
  • Visual Quality Enhancements
    • White Balancing
    • Contrast Stretching (Normalization)
    • Gamma Correction
    • Sharpening Filter
Low-Power with Low Latency
  • Minimal buffering for low-latency and low-power operation
    • Only five lines of buffering under its full configuration (two for Bayer filtering, and three for image sharpening)
  • Optimized, small implementation requires less than 15,000 equivalent gates
Performance
  • Fine pipeline allows processing up to over 150 Mpixels/sec even in low-end silicon
Input/Output Formats
  • 10bit/sample Raster-Scan Bayer Input, 8bit/Sample-Raster-Scan YUV Output
  • Up to two Mpixels, optionally extendable for higher resolution
Maturity
  • Robustly verified and production proven

Partner with us

Visit our new Partnership Portal for more information.

Submit your material

Submit hot news, product or article.

List your Products

Suppliers, list and add your products for free.

© 2018 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted,
reposted, duplicated or otherwise used without the
express written permission of Design And Reuse.