The DCD BLCD32 core is a fully configurable, universal LCD/TFT display controller. It supports a wide range of resolution and enables both, horizontal and vertical synchronization parameters setup. The display pixel clock can be generated by an internal pixel clock divider based on the bus clock, or delivered to the core by a dedicated pin. Additionally there is a possibility of using an externally generated pixel clock. Polarization of the generated pixel clock, as well as synchronization signals, is configurable.
The DBLCD32 has a DMA capable master interface, which can be used to access a framebuffer placed directly in a system memory. Embedded DMA controller has configurable FIFO to store pixels data, which increases system throughput and performance. Transmission on the master interface is burst oriented and there is a possibility of defining the burst size limit.
Data fetched by the DMA interface can be translated to 24-bits RGB signals,depending on the selected color mode. There are three standard color modes supported: 24-bits True Color, 16-bits(5-6-5) High Color and 8-bits index color mode. Additionally, a 32-bit True Color is also supported, but the MSB byte of each four byte word is ignored. In case of the Indexed Color Mode the DBLCD32 is equipped with pixel palette RAM which is used to translate each byte from the display buffer into 24-bit RGB output. There are two different formats of color palettes available.
The core supports the page flipping mechanism, which enables the usage of multiple buffering totally without the tearing effect. There is also a set of programmable interrupts available related to both display synchronization and DMA status signals. The core is capable to work on both little and big endian systems. To increase the system performance and flexibility of usage, the DLBLCD32 can be configured in two possible optimization levels, to find a proper balance between a gate count and a critical path length.