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All Silicon IP

Overview

Production–proven tools that integrate with common EDA flows.

ACE works in conjunction with industry-standard synthesis tools, allowing FPGA designers to easily map their designs into Achronix Speedster®22i FPGAs.

ACE includes an Achronix-optimized version of Synplify-Pro from Synopsys. Achronix simulation libraries are supported by ModelSim from Mentor Graphics, VCS from Synopsys and Riviera-PRO from Aldec.

Standard RTL (VHDL and Verilog) input together with industry-standard simulation ensures that the Achronix design flow is straightforward for existing FPGA designers.

We are here to help and support your existing engineering teams.

Our excellent support, combined with our detailed documentation allows you to quickly onboard your team and jumpstart your project.

We also offer various one-day, on-site workshops in 4.5G/5G Radio Head DFE application, multicore CPU acceleration for server applications, ASIC integration flow or Achronix eFPGA programming software benchmarks.

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