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This H.264 Application Platform System integrates multiple IP cores with memory and software on a system prototyping board to enable off-the-shelf execution and evaluation of high-definition video compression. The H.264 encoder, and interface cores are implemented in an FPGA on a commercial board that has onboard RAM. The board connects to a Windows host PC via a PCI Express interface. Raw video is fed to the board through a virtual RAM drive, compressed, and passed back to the PC for storage and viewing. The system can process up to 1080p video at 30 frames per second. Custom software provides a graphical user interface (GUI) for easy setting of H.264 compression parameters. It also manages video streaming, driver access, hardware control, and multitasking.

Block Diagram


Provides a complete, ready-to-use hardware/software package for H.264 evaluation, proof of concept, or product development quick start.
  • Processes up to 1080p video (1920 x 1080 pixel fames) at up to 30 fps.
  • Enables easy evaluation of and experimentation with H.264 video encoding using one own images and video.
  • Provides a fast PCI Express interface to host computer (MS Windows 7, Vista, and XP).
  • Integrates multiple CAST IP cores:
    • H264-BP-E H.264/AVS SD & HD Video Encoder Core
    • CPXP-EP PCI Express Endpoint Controller Core
    • CCBB-AHB CAST AHB Compression Core Bus Bridge
  • Built on commercial prototyping boards with Altera or Xilinx FPGAs:
    • Altera Stratix IV GX FPGA Development Kit
    • with Xilinx Virtex-5 FPGA for IP
  • Includes additional hardware as required:
    • PCIe PHY Daughter Board
    • PCIe Cable with ExpressCard Adapter
    • FPGA Configuration Module (e.g., System ACE)
  • Includes essential software:
    • MS Windows Kernel-Mode Driver
    • GUI Control and Streaming Software
    • RAM Drive virtual disk utility to achieve input transfer rate sufficient for reading uncompressed HD video


The H264-AP is available with soft cores (synthesizable HDL) or firm cores (netlists) for FPGA technologies, and includes everything required for successful implementation.:
  • HDL (VHDL or Verilog) RTL source code or netlist
  • Synthesis scripts
  • Place & route scripts
  • MS Windows Kernel-Mode driver
  • GUI Control and Streaming software
  • Hardware as appropriate (board, PCIe PHY, PCIe cable with ExpressCard Adapter, System ACE)
  • Comprehensive user documentation for the system and for each core, including detailed specifications, a system integration guide, and a demo guide

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