www.design-reuse-embedded.com
You are here : design-reuse-embedded.com  > Design Platform  > Power Management Platform
Download Datasheet        Request More Info

Overview

Chip designers waste too many energy-saving opportunities with conventional power management approaches because they can t easily expose them, nor transition circuit states fast enough to take advantage of them. The ICE-Grain family of Energy Processing Units (EPUs) exploits circuit idle moments - those periods of time when circuits are not needed for productive work - to make power state transitions up to 500 times faster than conventional approaches while supporting simultaneous switching of an unlimited number of power grains.

ICE-Grain EPUs are hardware subsystems that manage and control circuit idle moments to minimize energy consumption and maximize power savings. These EPUs are user-configurable and scalable to meet design specifications while providing automated RTL and UPF code generation, verification, and design flow integration with industry-standard EDA environments. ICE-Grain EPUs co-exist and interoperate with conventional approaches to on-chip power management.

ICE-Grain EPUs derive their speed advantage by applying distributed hardware to the tasks of identifying idle and active moments, sequencing through power states and directly controlling the power minimization circuits. Faster switching allows the EPU to exploit shorter idle moments and choose deeper power states. When the design is partitioned into many power grains, EPUs scale to process millions of power state transitions per second (MSPS) in parallel, hundreds of times more than software-based approaches leveraging dedicated microcontrollers, while delivering deterministic responsiveness. The more idle moments an EPU processes, the higher the MSPS number and the greater the energy savings on chip.

As the first products implementing the reprogrammable ICE-Grain Power Architecture®, ICE-G1, ICE-G3 and ICE-P3 aggregate both active and static power savings techniques into an automated methodology that users can scale and repeat from their first design to its derivatives to extract more savings through successive refinement.

Block Diagram

Features

  • Maximizes Power Savings Opportunities
    • Distributed architecture and automation enable fine-grained power partitioning to expose idle moments.
    • Aggregation of savings techniques like DVFS, clock/power gating and retention switching ensures minimum energy consumption.
  • Minimizes Energy Consumption
    • Autonomous EPU identifies, sequences, and controls power state transitions up to 500X faster than conventional CPU-based approaches.
    • Distributed power grain and cluster controllers provide parallel operation and deterministic responsiveness.
    • EPU delivers more than 10 MSPS to exploit idle moments and save energy.
  • Adapts to Operating Conditions
    • Reprogrammable architecture supports optimization to varying operating modes.
    • Internal monitors enable observation-driven adaptation to the end system.
  • Automates Energy Control
    • Powerful UI abstracts control complexity into user-defined power states with automated derivation of grain controllers.
    • Imports and exports RTL and IEEE-1801 UPF views to ensure correctness.
  • Speeds Integration
    • Flexible grain controllers adapt to customer-defined clocking, reset, isolation, retention and power gating approaches.
    • Timing-friendly internal signaling simplifies physical implementation.
    • Architecture provides easy interfacing to existing power control implementations.

Partner with us

Visit our new Partnership Portal for more information.

Submit your material

Submit hot news, product or article.

List your Products

Suppliers, list and add your products for free.

© 2018 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted,
reposted, duplicated or otherwise used without the
express written permission of Design And Reuse.