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The VC-2 LD (Low Delay) Codec is ideally suited for ultra-low latency video transmission. The low complexity of the algorithm allows cost-effective compression of the video stream. A typical use case of the VC-2 LD codec is the reduction of the bandwidth required to transport HD, 4K and high frame rate video signals. The VC-2 Low Delay compression algorithm is a simple wavelet-based intra-frame codec. The algorithm is described in the SMPTE 2042 standard, VC-2 Video Compression . The algorithm is especially designed to achieve low latency. Due to its low complexity, the VC-2 LD encoder and decoder do not require any external memory. The resource usage being very low, it can be easily integrated in existing designs and low-end Altera and Xilinx FPGA s.


  • Video Transport over IP networks
  • High Resolution video over SDI cabling
  • Camera sensor encoding with VC-2 LD
  • Image and video storage with VC-2 LD
  • The VC- 2 LD codec is suitable to any markets where video is present (Broadcast, pro AV, defense, industrial, medical and automotive)

Block Diagram


  • High Quality Profile
  • Visually lossless and mathematically lossless
  • Ultra low latency
  • Low complexity codec
    • No external memory
    • Low resource usage
  • Unrestricted frame resolution
  • Bit-depth up to 16-bit
  • Color samplings (4:4:4, 4:2:2, 4:2:0 and monochrome)
  • Progressive and interlaced formats
  • Constant Bit Rate
  • SMPTE 2042 standard
  • Xilinx, Altera and ASIC
  • Patent Free codec

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