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CEVA-XM6 is the 5th generation imaging and computer vision processor IP from CEVA, designed to bring deep learning and artificial intelligence capabilities to low-power embedded systems, targeting mass market intelligent vision applications.


  • Superior performance for optimal real time execution in time-critical use cases, such as autonomous driving, sense and avoid drones, virtual and augmented reality, smart surveillance, smartphones, robotics and more.
  • Low power consumption to meet the demand of battery-powered devices of all sizes, including use cases with multiple vision engines.
  • Flexible and scalable to efficiently address the many use cases and the constantly evolving domain of intelligent vision.
  • Small die size for a cost-effective solution required to address mass market applications.
  • Augmented by the CDNN toolkit, a collection of hardware and software IPs that streamline the implementation of deep learning in embedded systems
  • Addressing every aspect of creating a superior vision system with minimal effort, allowing our customers to focus their development on product differentiation.

Block Diagram


The CEVA-XM6 introduces a range of architectural innovations and enhancements that deliver breakthrough performance for neural networks and advanced computer vision processing
  • Innovative vector processor unit (VPU) architecture - ensuring above 95% MAC utilization.
  • Enhanced Parallel Scatter-Gather Memory Load Mechanism - further improving the performance of vision algorithms, including SLAM and depth mapping
  • Sliding Window 2.0 - This patented mechanism takes advantage of pixel overlap in image processing and helps to achieve higher utilization for a wider variety of neural networks and cope with the increasing complexity of these networks
  • Optional 32-way SIMD vector floating-point unit that includes the IEEE half precision standard (FP16) and major non-linear operations enhancements
  • Other improvements include an enhanced 3D data processing scheme for accelerated CNN performance, a 50% improvement in control code performance versus the CEVA-XM4, a new scalar unit which further reduces code size, multi-core and system integration support

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