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The CT1008-TCP/IP is an FPGA Synthesisable 10 or 25Gbit Ethernet TCP server/client in a lean and fast, all-RTL solution

The IP block provides an easy path to integrate protocols based on TCP/IP -Server/Client/both in an FPGA using a minimum of FPGA resources

Valuable resources in your application are freed up by the TCP/IP which offloads the entire TCP stack onto an FPGA logic

Applications such as a Host CPU or another FPGA function can take advantage of these features and quickly add blazing fast 10 or 25G Ethernet connectivity

Block Diagram


  • 1 to 256 Simultaneous connections
  • Server/Client roles, configurable per connection
  • Hash table based filtering for minimum latency
  • Low-jitter sustained high throughput performance
  • Programmable per connection receive/congestion window
  • Monitoring function, "bump-in-the-wire" inspection, non-intrusive packet sniffing
  • Cut-through mode for absolute highest throughput and lowest latency
  • Store-and-Forward mode ensures ultimate safety in verified data to and from the application.
  • Low-latency TX: 10clk (64ns) RX: 10clks (64ns) (depending on compile time options)
  • 64-bit AXI4 stream @ 156 MHz

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