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Low-density parity check (LDPC) technology provides the high level of error correction needed for today’s low cost and high density flash memories. Symbyon’s patented solution is the most area and energy efficient LDPC implementation. It has support for soft data that estimates how likely each bit is correct. This information can greatly extend the useful life of a flash chip. This IP is fully configurable with support for multiple codeword rates and lengths using the same implementation.

Customizable parameters include codeword rate and length, parallelization, number of soft bits read from the flash memory and utilized by the LDPC detector. The Symbyon LDPC Encoder/Decoder IP core is delivered in Verilog RTL, which can be implemented in an ASIC or FPGA. It is fully tested and verified on FPGA and in software.


  • Patented decoder architecture with minimum gate count and lowest power consumption
  • Soft data support for enhanced error correction performance
  • Optimized multi-rate decoding to minimize latency and maximize error correction
    • Accomplished by moving from higher rates to lower rates when approaching flash end-of-life
  • Validated IP reduces Time-To-Market
  • Smooth integration with NAND Flash controller

Block Diagram


  • ECC for MLC, TLC, and 3D NAND Flash
  • Patented LDPC technology with minimum gate count and lowest power consumption
  • Fully Configurable
    • Simultaneous support for different code rates (parity bits)
    • Various codeword lengths
    • High parallelism for high datarate applications (ex., 6.4 GB/s at 800 MHz)

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