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Overview

An ADC-based long-reach (LR) 112G SerDes PHY solution providing leading-edge performance and power efficiency for next-generation networking and hyperscale data center applications.

The Rambus 112G LR MPS PHY is a comprehensive IP solution designed to provide best-in-class performance across challenging long-reach signaling environments for next-generation networks and hyper-scale data centers. It supports PAM-4 and NRZ signaling and data rates from 10.31 to 106.25 Gbps across copper and backplane channels with more than 35dB insertion loss. At the heart of the 112G MPS architecture is an ADC operating at 56 GS/s that allows for adjustable power and improved performance while providing low BER.

Block Diagram

Tech Specs

Target Process Node7nm FinFet

Features

  • Supports up to 4 duplex lanes and data rates from 10.3 to 106 Gbps
  • Embedded micro-processor enables firmware-controlled PMA configuration, initialization and adaptation for maximum flexibility and minimum ASIC integration effort
  • RX front end with on-chip capacitors supports both AC-coupled and DC-coupled channels
  • Configurable architecture enables power saving models for low and medium loss channels
  • Flexible ASIC interface for sharing impedance codes among multiple PMAs and reducing the number of external reference resistors for on-chip impedance calibration
  • Programmable TX/RX equalizers including:
    • 4-tap transmit FFE (2-tap pre-cursor taps, main tap and 1 post-cursor tap) for extended channel reach
    • Combined 14dB peaking gain of analog front end with CTLE
    • Multi-tap digital FFE and DFE
  • A centralized LC-PLL supports a wide range of reference clock frequencies and lane operating frequencies
  • Differential reference clock inputs selectively sourced from dedicated pins or internal ASIC interface pins
  • Direct register control available for all PMA functions
  • Flexible layout supports placement along all ASIC edges
  • PMA is spec compliant across a wide operating junction temperature range (-20 to 105 °C). PLLs, bias circuits, and data paths are functional between -40 to 125 °C
  • In-situ real-time monitoring and receive data eye voltage histogram
  • Built in PRBS generators and checkers along with custom pattern generation
  • ATPG Mux Scan support for digital logic
  • IEEE 1149.6 JTAG boundary scan for SerDes pins
  • Built-in BER monitor including a 40-bit counter to count the total number of bits received and a 30-bit counter to count the total number of errors detected by a pattern checker
  • Internal serial loopback and parallel loopback support
  • Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port

Deliverables

  • PMA hard macro and design kit
    • Verilog models
    • LEF abstracts (.lef)
    • Timing models (.lib)
    • CDL netlists (.cdl)
    • ATPG models
    • IBIS-AMI models
    • GDSII layout
    • DRC and LVS reports
  • Datasheet
  • SoC integration guide
  • Optional design integration and bring-up support services

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