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The Universal Ethernet MAC/PCS offers industry s lowest latency, power, and size. The highly flexible IP Core can be customized to speeds from 1 Gbps to 400 Gbps and targeted to both FPGA and ASIC platforms. The innovative, high-speed MAC/PCS design can be automatically ported from the FPGA to ASIC platform with dramatic reductions in latency, power consumption, and logic size. All Tamba Gigabit Ethernet IP Cores are based on an innovative Unified Architecture. The unified architecture allows all Tamba IP Cores to have the proven high quality and a common asynchronous system-side interface. The asynchronous system-side interface decouples Ethernet MAC clock domains from the native system clock domains, and thus enables seamless integration of Tamba IP Cores with the customers' existing designs. In addition, the Unified Architecture enables seamless exchange of data among different types of I/O ports using Tamba's proprietary Auto-Bridge™ technology.


Lowest latency core on the market, e.g;

  • 10GE "FIFO+MAC+PCS" ~10ns in 28nM ASIC
  • 10GE "FIFO+MAC+PCS" ~20ns in FPGA

Lowest gate count core on the market.

Large timing margin: cores will often run in the slowest speed grade saving money, and compile with push button ease in minutes.

Single code base for all versions, which drastically reduces internal support and learning curve.

Customizable synthesis for any speed/target technology. FPGA or ASIC, 65nM or 14nM ASIC node the RTL can be configured to add or drop pipeline stages to yield the best performing core for the target technology.

Block Diagram


  • 1 to 400Gbps
  • Single RTL code base supports all speed variations.
  • Supports Altera, Xilinx, Microsemi FPGA and ASIC.
  • Full MAC layer and Reconciliation sub-layer implementation compliant with IEEE802.3
  • Configurable IPG with DIC from 1 byte to 48 bytes. Note, 12 bytes is the standard, and the default mode.
  • Configurable Preamble size and contents
  • Configurable Transmit Pad insertion.
  • Port and Class of Service Pause Frame support
  • CRC-32 insertion and checking at line-rate
  • 100% bandwidth through implementation of Deficit Idle Counter (DIC)
  • Full handling on transmit & receive FIFO overflow & underrun.
  • Jumbo frame support
  • Transmit and Receive Statistics Vector
  • Local Loopback
  • PHY error and fault signaling provided by Reconciliation sub-layer
  • Frequency independence; the Tx and Rx MAC can be gapped down to any logical bandwidth

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