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Overview

The Xelic XA304 Application supports the mapping of dual Transcoded Gigabit Ethernet signals into ODU0 frames and ODTU01 multiplexing for ODU1/OTU1 frame rate transport. As shown in the block diagram below, the XA304 application contains two Gigabit Ethernet Transcoder/OPU0 Mappers (XCO0M), two ODU0 Framers (XCO0) with GMP processing, an ODTU01 Multiplexer (XCO01MX) and an ODU1/OTU1 Framer (XCO1). Independent XA304 Transmit and Receive Data Path Processors are used and share a 16-bit generic register interface to provide internal memory mapped access for configuration and performance monitoring. A client side Gigabit Ethernet clock is used for 8B/10B processing of incoming Gigabit Ethernet signals. The remaining XA304 Transmit Processor data path operates off a common ODU1 or OTU1 rate clock using a data valid scheme. Likewise, a client side Gigabit Ethernet clock is used for 8B/10B processing of generated Gigabit Ethernet signals. The remaining XA304 Receive Processor data path uses a common ODU1 or OTU1 rate clock with a data valid scheme. This application has been verified through extensive simulation testing and hardware validated on Xelic evaluation platforms using industry standard test equipment. The XA304 application can be extended to include the mapping of several other client signals into ODU0 frames including SONET/SDH STS-3, STS-12, Video, 1 Gigabit Fibre Channel, etc. The GMP processor for each ODU0 framer can be configured to process any rate that will fit into an OPU0 container.

Features

Implements 16-bit register interface for programming of internal registers.
Complies with ITU-T G.709 and ITU-T G.798 specifications.
Supports transmit and receive facility and terminal loopback configurations.

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