The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD panel. In an ASSP, ASIC, or FPGA, typically, the microprocessor is a ARM or MIPS processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.