Bangalore Event
April 5, 2017
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Santa Clara Event >> January 26, 2017 |
Bangalore Event >> April 5, 2017 |
Shanghai Event >> September, 2017 |
Grenoble Event >> December , 2017 |
D&R IP-SoC India - Bangalore (April 5, 2017)
Supported by:
Where :
Hotel Park Plaza, 90/4, Outer Ring Road, Marathahalli village, Bengaluru, Karnataka 560037, India
First announced talks
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| 9:00 |
Welcome : IP market status reminder 20th D&R anniversary initiative : D&R announces the opening of a FPGA Market Place and IP shop dedicated to FPGA IP and SoC  By Gabriele SaucierCEO, Design And Reuse |
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| 9:30 |
ESDM and IOT: State of the union in India By Venkatesh KumaranIndia Electronics & Semiconductor Association (IESA) |
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| 9:50 |
New Business models in Semiconductor Industry for Interconnected world By Samir PatelCEO, Sankalp Semiconductor |
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| 10:10 |
Role of 3rd Party IP Selection and Integration in ASICs By Naveen Narang Open Silicon |
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| 10:30 |
How to Jump Start Your ARM-based IoT Chip for Free By Kishore AmarnathARM |
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| 10:50 | Break | ||
| Session 1 - Designing on FPGA Chairman: Chris Dunlap (Xilinx) |
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| 11:15 |
Applications of Embedded FPGA and Techniques for Physical Design Integration By Abhijit AbhyankarFlexLogix |
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Artificial intelligence in FPGAs By Israr Sheikh FAE Manager, Intel |
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FPGA Based High Bandwidth PCIe DMA IP Implementation By Ravi JavaliAtria Logic |
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HW-SW co-design on Zynq SoC By Shashank PujariPimpri Chnichwad College of Engineering |
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| 12:30 | Lunch | ||
| 13:30 | Session 2a - From IP to SoC to System Chairman: Prakash Eswaran (Sankalp Semiconductor) -"USB Type-C Multi-port Power Delivery IP" by Rakesh Kumar Polasa and Abhishek D Sardeshpande (Siliconch) -"GPU based Hybrid Realtime HEVC Encoder" by Mohammad Aziz (Atria Logic) -"Accelerating Typical Image Processing Applications using ARC EM Processors" by Abhishek Bit (Synopsys) -"Improving Inter Integrated Circuits: from sensor hubs to platform management solutions" by Pratap Neelishetty (Synopsys) |
13:30 | Session 3a - Emulation and Verification Chairman: -"Importance of Emulation in Pre-Silicon Validation of SOC" by Shyam Ramaswamy (Test & Verification Solutions) -"Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP" by Vishnuvardhan Reddy Mandala (Synopsys) -"Realistic "X" modelling at Gate Level: Verilog BEHAVIOUR models for Standard Cells" by Pramod Gayakwad (NXP Semiconductors) |
| 14:30 | Break | ||
| 15:00 | Session 2b - From IP to SoC to System Chairman: Prakash Eswaran (Sankalp Semiconductor) -"Interlaken- High Speed Chip to Chip Interface IP supporting 1.2Tbps bandwidth and up to 56Gbps SerDes" by Devendra (Open Silicon) -"Method and Structure for reducing system Boot time on safety critical SoC containing ECC protected on-chip SRAM" by Akshay Bisht (NXP Semiconductors) -"Acheiving High Performance Serial Nor Memory Access Through "Execute-in-place" Feature" by Nishith Sharma (Synopsys) -"Context based Clock Gating Techinique for Low Power Designs of IoT Applications: A Designware IP Case Study " by Madhusudhan Prabhu (Synopsys) |
15:00 | Session 3b - Manager Session Chairman: -"IP Publishing" -"IP Packaging and Delivery Management - The Worldwide Standard for IP provider" -"You integrate IPs from many sources in your products?" -"You manage corporate wide a huge number of Software licenses?" by Gabriele Saucier (Design & Reuse) |
| 16:00 | Panel : IP Value on Programmable Devices or Embedded Programmable Blocks : Future and Vision
Moderator: Venkatesh Kumaran (IESA)
With the participation of : Gabriele Saucier (CEO of D&R), Samir Patel (CEO of Sankalp), Chris Dunlap (IP & Solutions Marketing Direcor at Xilinx), Abhijit Abhyankar (VP Silicon Engineering at FlexLogix), Sachin Jadhav (Technical Lead, System Software at Open Silicon), Intel | ||
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