Panel Summary : IP Value on programmable Devices or Embedded programmable blocks: Future and Vision
In the last decade FPGA devices were often considered as limited to small Series or as "just" Asic prototyping vehicles . The technology evolution and their integration power increase are continuously opening a broader market space as end products. In parallel, more attention is given to embedded programmable blocks easily integrated in any ASIC technology and this may appear as an attractive alternative or complementary solution
IP (or Innovation) providers recognized as the vital seed of electronic systems commonly deploy first their skill on FPGA devices as they are not able to cope with the drastic cost of Asic technology (tools ,fab access...). Having proven their IP on FPGA, they will have to capture market attention, trigger business deployment and provide support in a global world. They may suffer from a low market pricing of FPGA IP, lack of innovation protection of soft IP and intractable worldwide marketing, sales and support channel deployment.
On their side, IP consumers may complain about an unreliable access to small IP providers with insufficient guarantee in terms of quality, follow up , viability of a provider company.
The panel will discuss these issues and lastly D&R expects feedback about its proposal to create a shared market and sales ecosystem for FPGA IP providers
Some questions to be addressed
- Q1: FPGA for prototyping or end products? still a challenge
- Q2 :Embedded programmable blocks is it the breaking innovation? Who will program embedded programmable blocks, the chip company or their customers?
- Q3 How to estimate the value of an IP on FPGA. Is it viable for IP providers? Do the designers just need FPGA proprietary, maybe Third party IP but no other IP?
- Q4. Have IP consumers easily access to innovative IP from FPGA providers? Can they easily evaluate, purchase and rely on a long-term support...
- Does D&R initiative as a virtual broker help to promote, consolidate, favor innovation for IP on FPGA?