Design And Reuse News Alert
May 23rd, 2019
In this issue
• Cut Off From ARM, x86, What CPU Architectures Can Huawei Use?
• Arm Deals Massive Blow to Huawei
• Taiwan's TSMC says chip shipments to Huawei not affected by U.S. ban

Asic Design Platforms
What's new in Interface IP and Processor IP
RISC-V Ecosystem
Sifive The RISC-V Revolution is Going Global!
We are coming to six cities in Europe in May, 2019.

Learn More...

Enterprise Platform
Artificial Intelligence and Machine Learning
New Achronix Ground-Breaking FPGA Family : Speedster7t
Optimized for
• Artificial Intelligence/Machine Learning
• High-Bandwidth Data Acceleration Applications
Manufactured on TSMC 7nm FinFET

Audio and Multimedia
China US Business war
Business News

Gyrfalcon Technology
Silicon proven CNN accelerator speeds time to market
with the best performance (TOPs) ratio to Power
• Suite of models & framework tools
• IP development tools
• AI for Edge and Cloud
Learn more...

D&R Welcomes its new partner

Interconnecting chiplets and chips
• Silicon-proven SerDes IP
• Ultra low power and area
• Multi-standard compatible
• Extensive IP portfolio

Hot at IP SoC Santa Clara 2019

SiliConch Systems at IP SoC Santa Clara 2019
Shubham Paliwal, Co-Founder & Micro Architect, SiliConch Systems

Next Generation of SoC Design flow -- From Atoms to System solutions
Babak Taheri, CTO and EVP of Products, Silvaco, Inc.

Mentor at IP SoC Santa Clara 2019
Farzad Zarrinfar, Managing Director, IP Division, Mentor, a Siemens Business

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