Design And Reuse News Alert
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July 18th, 2019
In this issue
• AI At The Very, Very Edge
• Arm Flexible Access gives chip designers the freedom to experiment and test before they invest
• Semi Content in Electronic Systems Forecast to Drop to 26.4% in 2019
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Design & Reuse
Registration open for IP SoC China 2019

 Where : Shanghai     When: September 12th
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And book your calendar for IP SoC Grenoble Dec. 3-4th

Foundry Business News
Design Kit
Wave computing MIPS I6500 Multiprocessor for Scalable Parallel Processing Performance
• Scalable, coherent cluster of up to 6 CPU cores
• Multi-threading for efficient real-time control
• Plus ASIL-B qualified documentation package
Learn More

New IP and SoC
Read More
Design Tool and Design platform
RISC-V Ecosystem
Artificial Intelligence and Vision in the Semiconductor world
Business News



D&R PARTNER SPOTLIGHT
Cadence

Tensilica DNA 100 Processor IP
• Industry-leading performance
• Power efficiency for edge AI applications
• Optimized for edge neural network inference apps
Learn more >>

D&R Welcomes its new partner
Socionext
Safe Connect Systems
Provider of added value connectivity IP-cores
• For demanding applications over Ethernet
• Making machine and vehicles more efficient, secure and evolutive

Hot at DAC 2019


Silvaco at DAC 2019
Graham Bell,Sr. Director of Marketing,


Moortec Semiconductor at DAC 2019
Ramsay Allen, VP of Marketing


SiliconGate at DAC 2019
Floriberto Lima, President & CEO, SiliconGate


Sankalp Semiconductor at DAC 2019
Samir Patel, CEO


Synopsys at DAC 2019 : Automotive and Artificial Intelligence
Ron DiGiuseppe, Automotive IP Segment Manager at Synopsys


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