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Cadence Achieves First PCI Express 2.0 and PCI Express 3.0 Compliance for TSMC 16nm FinFET Plus Process

Multi-protocol PHY supports PCI Express 2.0, PCI Express 3.0, USB 3.0 and SGMII specifications

SAN JOSE, Calif., Feb. 25, 2015 – 

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its multi-protocol Serializer/Deserializer (SerDes) PHY IP for PCI Express® (PCIe®) 2.0 and PCIe 3.0 technology for TSMC's 16nm FinFET Plus (16FF+) process have passed PCI-SIG® compliance testing. The complete solution of PHY and controller achieved compliance just 12 months after the announcement of the 16FF+ process. Achieving PCI-SIG compliance further boosts designers' confidence that the Cadence IP will operate to the specification, when integrated in their system-on-chip (SoC) designs.

For more information on Cadence IP for PCIe offerings, please visit http://ip.cadence.com/ipportfolio/ip-portfolio-overview/interface-ip/pci-express-ip.

"As a PCI-SIG member for more than 10 years, Cadence has played a role in promoting the adoption of PCIe technology," said Al Yanes, president and chairman of PCI-SIG. "By participating in the compliance program, Cadence is helping to ensure PCIe ecosystem interoperability."

The multi-protocol PHY enables designers to make performance and system cost tradeoffs while reducing risk and shortening design cycles. The support of multiple protocols enables creation of flexible SoCs that can be configured to different standards via software, extending the application of a single tapeout. Design schedules and cost are minimized by reducing the number of PHYs to evaluate, integrate, and characterize.

"PCIe 3.0 and PCIe 2.0 compliance was achieved with first 16FF+ silicon. The early availability of these products enables our customers to tapeout their leading-edge mobile, storage and enterprise designs sooner and with reduced risk," said Osman Javed, product marketing director at Cadence. "These flexible multi-protocol solutions provide customers a unique combination of SoC differentiation and future proofing."

"As part of its successful PCIe compliance testing, Cadence utilized the leading-edge PCIe 2.0 and PCIe 3.0 test and development tools from Teledyne LeCroy," said Joe Mendolia, vice president of marketing at Teledyne LeCroy. "This is the latest example of many years of the close relationship between the two companies on comprehensive compliance testing that enables designers to confidently integrate high-speed PCIe interfaces into their SoCs."

About Cadence Design Systems, Inc.

Cadence Design Systems is a leading global EDA company. Cadence customers use our software, hardware, and services to overcome a range of technical and economic hurdles.

Our technologies help customers create mobile devices with longer battery life. Designers of ICs for game consoles and other consumer electronics speed their products to market using our hardware simulators to run software on a virtual chip long before the actual chip exists. We bridge the traditional gap between chip designers and fabrication facilities, so that manufacturing challenges can be addressed early in the design stage. And our custom IC design platform enables designers to harmonize the divergent worlds of analog and digital design to create some of the most advanced mixed-signal system on chip (SoC) designs. These are just a few of the many essential Cadence solutions that drive the success of leading IC and electronic systems companies.

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