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Cadence Introduces Innovus Implementation System, Delivering Best-in-Class Results with Up to 10X Reduction in Turnaround Time

SAN JOSE, Calif., Mar. 10, 2015 – 

Cadence Design Systems, Inc. (NASDAQ: CDNS) today unveiled Cadence® Innovus™ Implementation System, its next-generation physical implementation solution that enables system-on-chip (SoC) developers to deliver designs with best-in-class power, performance and area (PPA) while accelerating time to market. Driven by a massively parallel architecture with breakthrough optimization technologies, the Innovus Implementation System provides typically 10 to 20 percent better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes and established process nodes.

For more information on the Innovus Implementation System, please visit www.cadence.com/news/innovus.

The Innovus Implementation System was designed with several key capabilities to help physical design engineers achieve best-in-class performance while designing for a set power/area budget or realize maximum power/area savings while optimizing for a set target frequency. The key Innovus capabilities to achieve this include:

The Innovus Implementation System also offers multiple capabilities that boost turnaround time for each place-and-route iteration. Its core algorithms have been enhanced with multi-threading throughout the full flow, providing significant speedup on industry-standard hardware with 8 to 16 CPUs. Additionally, the Innovus Implementation System features the industry's first massively distributed parallel solution that enables the implementation of design blocks with 10 million instances or larger. Multi-scenario acceleration throughout the flow improves turnaround time even with an increasing number of multi-mode, multi-corner scenarios.

In addition to providing best-in-class PPA and optimized turnaround time, the Innovus Implementation System offers a common user interface (UI) across synthesis, implementation and signoff tools, and data-model and API integration with the Tempus™ Timing Signoff solution and Quantus™ QRC Extraction solution. Together these solutions enable fast, accurate, 10nm-ready signoff closure that facilitates ease of adoption and an end-to-end customizable flow. Customers can also benefit from robust visualization and reporting that enables enhanced debugging, root-cause analysis and metrics-driven design flow management.

"At Arm, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets," said Noel Hurley, general manager, CPU group, Arm. "We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our Arm® Cortex®-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target. Based on our results, we are confident that the new physical implementation solution can help our mutual customers deliver complex, advanced-node SoCs on time."

"Customers have already started to employ the Innovus Implementation System to help achieve higher performance, lower power and minimized area to deliver designs to the market before the competition can," said Dr. Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. "The early customers who have deployed the solution on production designs are reporting significantly better PPA and a substantial turnaround time reduction versus competing solutions."

About Cadence Design Systems, Inc.

Cadence Design Systems is a leading global EDA company. Cadence customers use our software, hardware, and services to overcome a range of technical and economic hurdles.

Our technologies help customers create mobile devices with longer battery life. Designers of ICs for game consoles and other consumer electronics speed their products to market using our hardware simulators to run software on a virtual chip long before the actual chip exists. We bridge the traditional gap between chip designers and fabrication facilities, so that manufacturing challenges can be addressed early in the design stage. And our custom IC design platform enables designers to harmonize the divergent worlds of analog and digital design to create some of the most advanced mixed-signal system on chip (SoC) designs. These are just a few of the many essential Cadence solutions that drive the success of leading IC and electronic systems companies.

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