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Tiempo Secure TESIC-SC dual interface microcontroller is ready for evaluation and software development

Grenoble, France, Mar. 30, 2015 – 

Tiempo Secure, a semi-conductor specialist focusing on high-end secure products, introduces its dual interface secure microcontroller TESIC-SC built around its patented asynchronous design technology. As Tiempo secure chips are clockless, they are able to run faster, especially in contactless mode, as they can adapt permanently their execution speed to the strength of RF communication. This way they ensure a significantly faster execution, thus reducing dropped transaction issues and bringing to software developers the ability to integrate additional security features.

Thanks to its faster speed and higher security, Tiempo Secure TESIC-SC is ideally suited to develop EMV payment applications, open loop (pay at the gate) transport applications and e-government documents satisfying all robustness, performance and security requirements of application issuers. In order to assure customers of its security, Tiempo TESIC-SC secure dual interface microcontroller is undergoing Common Criteria EAL 5+ and EMV certifications.

Tiempo Secure TESIC-SC is manufactured at LFoundry Avezzano, Italy, on a 110 nm process with embedded 90 nm flash. Thanks to a one-stop shop agreement with LFoundry, Tiempo Secure TESIC-SC will be available directly from LFoundry as tested dice. LFoundry provides a complete and secure supply chain that will be compliant with Common Criteria EAL5+ within this year.

Serge Maginot, CEO Tiempo Secure declares: "With the sample availability of TESIC-SC, Tiempo has reached an important milestone: our customers are currently testing the product and porting their OS to make sure they are ready to take advantage from the unique benefits of our product when TESIC-SC reaches mass-production stage, early 2016."

Tiempo Secure TESIC-SC is currently available as samples for smart card vendors to develop, port and test their operating systems and application software. It will be available as mass-production from early 2016.

About Tiempo

Tiempo offers a technology for the design of asynchronous and delay insensitive integrated circuits

Tiempo asynchronous circuits are fully clockless, meaning that they are self-controlled and their behavior is governed by signal transition handshakes and signal levels memorization

Because the circuits do not rely on a knowledge of timing, functional correctness is ensured regardless of any actual delay through gates and wires. This makes Tiempo s circuits very resistant to perturbations that traditionally impact timing, such as the manufacturing process, or changes in voltage or temperature

Tiempo implementation allows designs with both ultra-low power and high performances

Tiempo technology can be described with high-level models, in standard language and implemented using an optimized high-level synthesis tool from Tiempo, called Asynchronous Circuit Compiler (ACC). The tool accepts as input SystemVerilog models and generates an optimized Verilog gate-level netlist.

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