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High-level synthesis comes of age with SDSoC

by Adam Taylor - Embedded.com, Jul. 27, 2015 – 

If you have been following my ramblings on the Zynq over the years you will notice that the last few weeks I have focused upon a new tool from Xilinx called SDSoC. This tool has been developed to open up SoC and MPSoC capabilities for the first time to embedded system designers in a familiar environment. What this really means is we can develop our embedded application in an eclipse IDE using C, C++ or System C.

To me this is important as the Zynq is a device every embedded system designer should be familiar with and considering for their application. At its heart the Zynq is not a FPGA with embedded processors -- like previous generations of FPGA with Power PCs -- but a true embedded processor with very flexible interfacing capabilities (DDR, CAN, UART, USB, Giga Bit Ethernet, SPI and I2C to name a few). What separates the Zynq from other embedded processors is the attached programmable logic, and with SDSoC embedded system developers can exploit this pretty simply.

Those familiar with FPGA development may have noticed over the recent years the trend towards high level synthesis (HLS) and have experimented or developed with tools like Vivado HLS. HLS tools allow us to develop algorithms in C, C++ or System C and generate a synthesizable RTL netlist. Obviously this saves significant time in the development life cycle, as it is much faster to generate and verify algorithms in C than HDL.


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