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IP extracts on-chip performance data on TSMC 28HPC process
by Richard Wilson - Electronics Weekly, Aug. 05, 2015 –
Design reliability for sub-micron chips is highly dependent on physical parameters such as voltage and temperature. UK-based silicon intellectual property (IP) developer Moortec Semiconductor is offering chip designers process, voltage and temperature monitoring and optimisation IP for CMOS geometries such as 40nm, 28nm and FinFET.
The IP embeds monitors within System on Chip (SoC) designs for sensing die temperature, detecting logic speed and monitoring voltage supply levels.
The data can then be used to vary system clock frequencies and the voltage levels of supply domains.
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