Leti strains FD_SOI for more speed and less power

French semiconductor lab CEA-Leti has developed two techniques to induce local strain in FD-SOI (fully-depleted silicon on insulator) for circuits that will produce more speed at the same, or lower, power consumption, and improve performance, it claims.

By Steve Bush - Electronics Weekly, Dec. 08, 2015 – 

There is compressive SiGe for p-FETs and tensile Si for n-FETs.

"In addition to clearing the path to improved performance in FD-SOI technology, they preserve its excellent electrostatic integrity and its in situ performance tunability, due to back biasing," said Leti.

Local stress up to 1.6GPa can be achieved in the mosfet channel.

The first technique relies on strain transfer from a relaxed SiGe layer on top of SOI film.

Leti researcher Sylvain Maitrejean described it is In a recent eddition of the ECS Journal of Solid State Science and Technology. Short-channel electron mobility was boosted by more than 20 percent compared to unstrained reference. "This shows significant promise for enhancing the on-state currents of CMOS transistors and thus for improving the circuit's speed," said the lab.

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