PCIe 4.0 Heads to Fab, 5.0 to Lab

Next-gen debate--25 or 32 Gbits/s?

By Rick Merritt, EETimes,BRUSSELS, Jun. 28, 2016 – 

A handful of chips using PCI Express 4.0 are heading to the fab even though the 16G transfers/second specification won't be final until early next year. Once it gets all the details sorted out, the PCI Special Interest Group (PCI SIG) aims to start work in earnest on a 5.0 follow on running at either 25 or 32GT/s.

Cadence, PLDA and Synopsys demoed PCIe 4.0 physical-layer, controller, switch and other IP blocks at the PCI SIG's annual developer's conference here. They showed working chips, boards and backplanes that included a 100 Gbit/s Infiniband switch chip using PCIe 4.0.

It's been more than six years since the PCI SIG ratified its last major standard, the 8 GT/s PCIe 3.0. At the time it started the 4.0 version it thought it might be its last copper-based chip-to-chip interconnect. But since then Ethernet and Fiber Channel groups have pushed copper networking to 25 and 32 Gbits/s respectively.

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