Leti Develops 3d Network-On-Chip to Improve High-Performance Computing

French researchers at Leti, a CEA Tech institute, have announced a on-chip communications system that is intended to improve high-performance computing (HPC), with a scheme that is faster and more energy efficient than current solutions and is compatible with 3D architectures.

By Graham Prophet ,EETimes, Jul. 13, 2016 – 

Leti researchers, working in the " IRT Nanoelec " framework, boosted computing power and reduced energy consumption both by stacking chips on top of each other in a single package, and by placing the chips side by side on a silicon interposer. The chips, which have progressed from demonstrator to fabrication-ready, exchange data via a new communications network that is part of the network on chip (NoC) called 3D-NoC.

3D-NoC technology has been demonstrated with a homogeneous 3D circuit that is comprised of regular tiles assembled using a 4 x 4 x 2 NoC. It also features robust and fault-tolerant asynchronous 3D links, and provides 326 MFlit/s@ 0.66 pJ/bit. [Flit = Flow control dig it] It was fabricated in a 65nm CMOS technology using 1,980 TSVs (through-silicon vias - used to implement direct chip-chip 'vertical' connections) in a Face2Back configuration.

This second generation 3D-NoC technology has been integrated in the INTACT circuit developed in the IRT Nanoelec framework. The 3D circuit, currently in foundry, combines a series of chiplets fabricated at the 28nm FDSOI node and co-integrated on a 65nm CMOS interposer. The active interposer embeds several lower-cost functions, such as communication through the NoC and system I/Os, power conversion, design for testability and integrated passive components

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