Versatile FPGA IP Handing, Creation, and Packaging

The IEEE has ratified the 1735-2014 IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) specification.

By Joe Mallet, Synopsys, Jul. 21, 2016 – 

Many companies are under pressure to deliver products to market faster so as to achieve the longest time in the market. This has led companies designing complex FPGAs to move increasingly toward licensing IP cores for the majority of the building blocks forming their designs, as opposed to creating their own custom versions in-house. The increased use of third-party IP to help accelerate schedules is creating challenges for FPGA designers as they now find themselves needing an automated methodology for handling various IP flows.

Adding IP to a design can be confusing for FPGA designers, especially if the task is done without the help of tools and automation. This month's blog describes how Synplify FPGA synthesis software takes much of the guesswork out of importing IP into a project, regardless of its source.

Designers can incorporate interface IPs from Vivado for example, using a "white-box" approach, which involves generating a DCP file for the IP which is then used for Synplify synthesis and place and route. The DCP file for the IP will contain all of the original design constraints and therefore there should be no issues of 'dropping' or mistranslating a constraint. The timing constraint information will be used by synthesis for optimization of the design surrounding the IP block.

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