7nm processes at IEDM

In two late-news papers at IEDM 2016 in SanFrancisco on December 3rd to 7th, both TSMC and the IBM, Globalfoundries, Samsung alliance will take the wraps off their forthcoming 7nm FinFET technology platforms.

By David Manners-Electronics Weekly, Oct. 20, 2016 – 

A 7nm CMOS Platform Technology for Mobility from TSMC will present the world's first 7nm CMOS platform technology for mobile system-on-a-chip (SoC) applications, featuring FinFET transistors.

The technology can be optimized to emphasize either high performance or low power operation to accommodate the needs of diverse mobile applications. It features more than three times the gate density and either a speed gain (35-40%) or power reduction (>65%) versus the company's commercial 16nm FinFET process.

To demonstrate the technology, the researchers built a fully functional, low-voltage 256Mb SRAM test chip with full read/write functionality down to 0.5V, and the smallest SRAM cells ever reported (0.027um2).

Key features of the 7nm technology are an advanced patterning technique used with 193nm immersion lithography, an optimized fin width and profile, a raised source/drain epitaxial process that strains the transistor channel and reduces parasitics, a novel contact process, and a copper/low-k interconnect scheme featuring different metal pitches and stacks.

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