Flexlogic: Power and Performance Optimization for Embedded FPGA's
Tom Dillinger, Feb. 22, 2017 – Last month, I made a "no-brainer" forecast that 2017 would be the year in which embedded FPGA (eFPGA) IP would emerge as a key differentiator for new SoC designs (link to the earlier article here).
The fusion of several technical and market factors are motivating design teams to incorporate programmable logic functionality into their feature set:
- the NRE and qualification cost of a new SoC design is increasingly significantly, at newer process nodes; a single part number that can adapt to multiple applications is a significant cost savings
- many algorithms can be more efficiently implemented in logic than using code executing on a processor core; the flexibility of reconfiguring the algorithm logic to specific market requirements enables broader applicability
- new (on-chip and external) bus interface specifications are emerging, yet final ratification is pending -- a programmable logic IP block affords adaptability
Yet, field programmable logic implementations are often associated with higher power dissipation than cell-based logic designs. And, many of the applications for eFPGA technology are power-sensitive.
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