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Synopsys IC Validator Certified by Samsung for 10LPP Process Technology Physical Signoff


IC Validator delivers physical signoff in hours with massively parallel architecture

MOUNTAIN VIEW, Calif., May. 24, 2017 – 

Synopsys, Inc. (Nasdaq: SNPS) today announced that its IC Validator physical signoff solution has been certified by Samsung Electronics for physical signoff of all designs using the 10LPP process technology. Samsung's foundry customers now have access to the speed and scalability advantages of IC Validator and can verify their designs with full confidence. Synopsys In-Design technology also supports the runsets, which makes the same full-signoff accuracy checking available inside Synopsys' IC Compiler II physical implementation solution to deliver faster turnaround time and better timing results. The Samsung-certified runsets, including design rule checking (DRC), layout-versus-schematic (LVS) and metal fill technology files, are available immediately from Samsung.

"As DRC complexity increases with each new advanced technology generation, designers continue to need highly predictable results and fast DRC signoff," said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. "Synopsys and Samsung Foundry have collaborated on an extensive IC Validator tool as well as runset qualification, and met all of the certification requirements. Our foundry customers can now use IC Validator's fast analysis in both In-Design and signoff flows to maximize power, performance and area benefits of Samsung Foundry's 10LPP process technology."

IC Validator, part of the Synopsys Digital Design Platform, is a comprehensive and highly scalable physical signoff solution including DRC, LVS, programmable electrical rule checks (ERC), dummy fill and DFM enhancement. IC Validator is configured for today's extremely large designs by enabling both multi-threading and distributed processing over multiple machines to provide near linear runtime scalability benefits that extend to several hundreds of CPUs. IC Validator's massively parallel architecture utilizes smart, memory-aware load scheduling and balancing technologies to maximize utilization of mainstream hardware.

IC Validator is a companion product to IC Compiler II for In-Design physical signoff. In-Design allows place-and-route engineers to perform independent, timing-aware, signoff-quality analysis earlier―before the design is finalized and while correction can be automated. In-Design technology enables new high-productivity functionality within the place-and-route environment, including automatic DRC repair, improved timing quality-of-results with timing-aware metal fill, and rapid ECO validation. In-Design physical verification eliminates expensive iterations with downstream analysis tools and maintains a convergent design flow to physical signoff.

"Manufacturing complexity at advanced nodes challenges designers to deliver within schedule," said Bijan Kiani, vice president of product marketing for the Design Group at Synopsys. "Collaborating closely with leading foundries like Samsung ensures designers have timely access to performance optimized runsets. The runsets in concert with IC Validator's massively parallel architecture with near linear scalability provides our mutual customers the faster path to physical signoff closure."

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

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