5nm only a few years away, say IBM Research scientists

IBM together with its Research Alliance partners Globalfoundries and Samsung, and equipment suppliers have announced the development of a novel 5nm process, building silicon nanosheet transistors that will enable 5 nanometer chips.

By Julien Happich eeNewseurope, Jun. 07, 2017 – 

In a short introduction video, Nicolas Loubet, in charge of advanced epitaxy and sub-7nm device integration at IBM research explains that resulting increase in performance will help accelerate cognitive computing, the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today's devices, before needing to be charged.

Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering's NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7nm node technology.

The silicon nanosheet transistor demonstration, as detailed in the Research Alliance paper "Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET", and published by VLSI, proves that 5nm chips are possible, more powerful, and not too far off in the future.

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