Imec enables 5nm 2D FETs

Imec and Pisa University have performed the first material-device-circuit level co-optimization of FETs based on 2D materials for high-performance logic applications scaled beyond the 10nm technology node.

By David Manners-Electronics Weekly, Jul. 13, 2017 – Imec also presented novel designs that would allow using mono-layer 2D materials to enable Moore's law even below 5nm gate length.
2D materials, a family of materials that form two-dimensional crystals, may be used to create the ultimate transistor with a channel thickness down to the level of single atoms and gate length of few nanometers.

A key driver that allowed the industry to follow Moore's Law and continue producing ever more powerful chips was the continued scaling of the gate length. To counter the resulting negative short-channel effects, chip manufacturers have already moved from planar transistors to FinFETs.

They are now introducing other transistor architectures such as nanowire FETs. The work reported by imec looks further, replacing the transistor channel material, with 2D materials as some of the prime candidates.
In order to fit FETs based on 2D materials into the scaling roadmap, it is essential to understand how their characteristics relate to their behavior in digital circuits.

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