www.design-reuse-embedded.com

R&D: 40nm Split Gate Embedded Flash Macro With Flexible 2-in-1 Architecture


Hung-Chang Yu, Ku-Feng Lin, and Yu-Der Chih, Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan, ROC, Aug. 22, 2017 – 

Abstract: "This paper presents a 40nm 9.5Mb embedded flash (eflash) macro which can be partitioned as code storage and data storage in a single macro with enhanced read margin by using two design schemes: temperature adaptive reference scheme and flexible array partitioned scheme. By way of these design features, code storage memory achieves 140MHz read speed at the junction temperature of 160 C and data storage memory achieves 1M cycles endurance."

Click here to read more ...

 Back

Partner with us

Visit our new Partnership Portal for more information.

Submit your material

Submit hot news, product or article.

List your Products

Suppliers, list and add your products for free.

© 2017 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted,
reposted, duplicated or otherwise used without the
express written permission of Design And Reuse.