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RISC-V processor Mr Wolf arrives to solve problems, This processor core is written in System Verilog

February 06, 2018 // By Peter Clarke, eeNews

Feb. 06, 2018 – Researchers at ETH Zurich (Swiss Federal Institute of Technology in Zurich) and University of Bologna have received first silicon on their latest PULP-based IoT processor, codenamed Mr. Wolf after the character from the film Pulp Fiction who "solves problems."

PULP is a European parallel ultra-low processor initiative based on the RISC-V open-source processor instruction set.

Mr Wolf is a cluster based processor that features eight 32-bit RI5CY cores implementing the RISC-V ISA, according to Frank Kagan Gurkaynak, director of the microelectronics design center at ETH Zurich, who announced Mr. Wolf's arrival by way of an article on LinkedIn. Besides supporting standard (I)nteger, (C)ompressed, (M)ultiplication and 32-bit (F)loating-point extensions of RISC-V, it also provides our custom e(X)tensions for DSP operations. This processor core is written in System Verilog and is openly available from Github under the SolderPad License .

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