UltraSoC and Lauterbach RISC-V collaboration furthers vendor-neutral debug and development environment

February 20, 2018 -- UltraSoC and Lauterbach today extend their collaboratively delivered universal SoC (system on chip) development and debug environment with the addition of support for the RISC-V open-source processor architecture.

The inclusion of RISC-V continues the companies’ commitment to support all of the industry’s major processor architectures, and to provide best-in-class development tools for designers of heterogeneous systems that employ CPUs from multiple vendors.

UltraSoC recently became the first company to announce a processor trace solution for RISC-V. Combining this with Lauterbach’s TRACE32 suite gives RISC-V developers access to powerful debug, trace and logic analyzer tools that speed development and produce better overall quality of results.

“The use of heterogeneous architectures is growing rapidly, and the rise of RISC-V shows that more than ever, designers don’t want to be restricted in their architectural choices,” said Stephan Lauterbach, general manager of Lauterbach. “Our existing relationship with UltraSoC demonstrates the power of combining our respective sets of vendor-independent development tools – giving our customers the ability to choose both the IP they use in their chip, and the environment in which they develop and debug.”

Rupert Baines, CEO of UltraSoC added: “Across the industry there is rising excitement about the emergence of RISC-V as an open source processor. This is especially significant in heterogeneous multi-core architectures: engineers want the choice to ‘mix and ‘match’ cores and freely choose the best design for each application. Many development tools are tied to a vendor, or only operate within a narrow silo. Lauterbach and UltraSoC share a vision of tools that support engineers across all of a system, and support all architectures consistently.”

RISC-V IP Cores

TRACE32 is a set of modular development tools with integrated debug environments to support all common embedded microprocessor architectures with the tools’ debug, trace and logic analyzer capabilities.

UltraSoC embeds monitoring and analytics hardware within the SoC to speed development, cut costs and produce better performing products. This embedded, system-wide intelligence is non-intrusive and performs at wire speed. Combining Lauterbach’s TRACE32 and UltraSoC’s embedded IP gives design teams complete visibility of the real-world behavior of their devices – vital in accelerating development and particularly in easing the complicated debugging process, which can consume up to half of the total development effort for a typical SoC.

Both UltraSoC and Lauterbach are active members of the RISC-V Foundation and have a track record of delivery within the growing RISC-V ecosystem. In October 2017, Lauterbach announced its TRACE32 toolset was now offering debug capabilities for SiFive’s E31 and E51 RISC-V Core IP. Also in 2017, UltraSoC developed a specification for processor trace and offered it for adoption by the RISC-V Foundation as part of the open source specification. In January, the company announced the full availability of its RISC-V trace encoder solution for 32 or 64 bit designs.

UltraSoC and Lauterbach are exhibiting at Embedded World 2018 (Nürnberg, Germany, 27 February – 1 March).

• Lauterbach can be found in Hall 4, stand 210
• UltraSoC will be at the RISC-V Foundation booth in Hall 3A, booth 419
• UltraSoC CEO Rupert Baines will deliver a presentation at 10am, Tuesday 27^th February. The session will form part of the RISC-V Class, a full day of RISC-V focused discussions and presentations within the main conference

For more details on the event and to arrange a meeting with UltraSoC, visit the event page on the UltraSoC website.

UltraSoC and Lauterbach RISC-V collaboration furthers vendor-neutral debug and development environment

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