Configurability for Embedded FPGA Hard IP

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Mar. 27, 2018 – IP providers need to evaluate several complex engineering problems when addressing customer requirements – perhaps the most intricate challenge is the degree of IP configurability available to satisfy unique customer applications.

The development of configurable soft IP is a somewhat easier task. The hardware description language model is constructed to accept customer input parameter values that define specific micro-architectural features. For example, the width of a data bus could be abstracted in the soft IP model, or the number of instances of a component module in the IP hierarchy could be parameterized (as part of a 'generate' statement). Or, more simply, a set of static logical input values could select/de-select functionality in the model.

When the soft IP HDL is compiled and elaborated for simulation and logic synthesis, the specific parameter values and logic signal inputs define how the IP is configured. Although the soft IP model may utilize the parameterization features of the hardware description language, the IP provider is still responsible to verify the functional accuracy of the model over the range of acceptable parameter inputs.
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