Open-Silicon to Demonstrate its HBM2 IP Subsystem Solution for High Performance Computing Applications, and Showcase its Comprehensive IP Subsystem Solution for High-End Networking Applications at TSMC Technology Symposium 2018

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May. 19, 2018 – 

Open-Silicon, a system-optimized ASIC solution provider, will demonstrate its Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASIC SiPs in TSMC FinFET/CoWoS technologies, and showcase its Comprehensive Networking IP Subsystem Solution for High-End Networking Applications at TSMC Technology Symposium 2018, Boston, MA.

High Bandwidth Memory (HBM2) IP Subsystem Solution:

Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASIC SiPs in TSMC FinFET/CoWoS Technologies – This solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). The IP includes the controller, PHY and custom die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D interposer. Open-Silicon's HBM2 IP subsystem is silicon proven on a 2.5D HBM2 ASIC SiP (System-in-Package) platform. The platform is used to demonstrate the high-bandwidth data transfer rates of >2Gbps, and interoperability between Open-Silicon's HBM2 IP subsystem and HBM2 memory die-stack. http://www.open-silicon.com/high-bandwidth-memory-ip/

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