|
|
|
www.design-reuse-embedded.com |
|
Mobiveil and Avery Design Systems Partner to Provide SoC Designers a Fully Verified and Compliant PCIe 5.0 IP Solution
Mobiveil provides Design IP and Avery Design provides Verification IP for the latest PCIe 5.0 specification
MILPITAS, Calif. -- June 05, 2018 -- Mobiveil, Inc. today announced that it is partnering with Avery Design Systems to deliver a complete PCIe 5.0 IP solution for SoC designers needing a fully verified and compliant PCIe 5.0 interface solution for their designs. Mobiveil will provide root complex, endpoint, and switch configurations of controller IP with SR·IOV and ARI Support. Avery Design Systems will provide its comprehensive PCI-Xactor Verification IP solution portfolio.
About PCIe 5.0 Specification
PCIe 5.0 technology is the next generation in the Peripheral Component Interconnect Express standard defined by the PCI-SIG (PCI Special Interest Group). Its 32GT/s (Giga transfers per second) bandwidth will set the standard for speed targeting high performance applications such as artificial intelligence, machine learning, gaming, visual computing, storage and networking. The specification is slated for completion in 2019. PCIe 5.0 interface technology is expected to enable NVMe SSDs for enterprise and data centers to leverage the scalability of PCIe architecture both in higher bandwidth and lower latency
"Verification is often cited as demanding a large proportion of effort for any new design," said Chris Browy, SVP of WW Sales & Marketing at Avery. Our PCIe VIP implements a complete set of root complex, endpoint, switch, and SR-IOV models, protocol checkers, and compliance test suites utilizing a truly flexible and open architecture based on a 100 percent native System Verilog and UVM implementation to ensure an SoC designers PCIe 5.0 interface meets specification."
PCIe 5.0 IP CoresPCIe 5.0 Verification IPs
“By this collaboration between PCIe controller Design IP and Verification IP providers, SoC designers can have a total plug and play solution for adding PCIe 5.0 interface to their SoC designs, thus significantly reducing their time to market,” said Ravi Thummarukudy, Mobiveil CEO. Leveraging the intellectual property provided by these companies with specification compliant IP, designers can be assured of first-time success for the PCIe 5.0 interface in their designs.”
About Mobiveil, Inc.
Mobiveil is a fast‐growing technology company that specializes in the development of Silicon Intellectual Property (SIP), platforms and solutions for Storage, IoT and Communications markets. It leverages decades of experience in delivering high‐quality, production‐proven, high-speed serial interconnect SIP cores, and custom and standard form factor hardware boards to leading semiconductor companies worldwide. For the PCI Express-based Flash Storage market, Mobiveil developed NVMStor™, a subsystem comprised of GPEX™, the PCI Express Controller, NVM Express Controller (UNEX™), Universal Memory Controller (UMMC™) and a Flash Memory Controller. Mobiveil is headquartered in Milpitas, Calif., with engineering development centers located in Chennai, Bangalore and Hyderabad, India, and sales offices and representatives located in U.S., Europe, Israel, Japan, Taiwan and China.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, DP/eDP, HDMI, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at http://www.avery-design.com.
Back
Contact Us
Partnership Offers