Learning to Share - Embedded FPGA Timing Closure

Achronix Blog, Oct. 02, 2018 – 

When we start school as young children, one of the first lessons we learn is how to share (followed quickly by not running with scissors). As our Sr. Director of Systems Engineering, Kent Orthner, discussed at DAC this past June, sharing is also key when it comes to closing timing with embedded FPGAs (eFPGAs). With an eFPGA such as Speedcore IP, the task of closing timing is owned by two people: the ASIC designer, responsible for the design in the host ASIC, and the FPGA designer, responsible for the design targeting the FPGA. This situation is very analogous to how timing is closed on a PCB with an FPGA, where both designers need to cooperate and share the timing arc (and the FPGA design may change long after the board design is complete).

With an eFPFA, the programmable block may be inserted anywhere inside an ASIC, meaning that the individual eFPGA ports may connect to other blocks within the ASIC, or to buffers connecting to external pins. Further complicating the process is the fact that the design host in the eFPGA can and will change over time, possibly years after the ASIC was designed.

But rather than leaving it to design teams to develop a process, Achronix provides a defined methodology for achieving timing closure as well as support for industry-standard timing analysis tools. As Kent explained (video of his talk is here), there are two timing models (or modes) available to the design team: simple and advanced.

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