AndesCore N22 RISC-V Core Supports RV32IMAC or RV32EMAC Instruction Sets

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cnx-software.com, Aug. 28, 2019 – 

We covered Gigadevice GD32V general-purpose microcontroller with a RISC-V "Bumblebee" core last week, and I was informed that Andes Technology had recently introduced AndesCore N22 RISC-V "Bumblebee" IP core capable of supporting either RV32IMAC or RV32EMAC instruction sets.

A web search did not reveal any specific information about what "Bumblebee" RISC-V cores are exactly, or maybe it's in reference that many can be coupled in parallel. But that's just a small detail, let's check out in some details what AndesCore N22 core has to offer. The RISC-V core is designed for entry-level MCUs found in IoT devices and wearables, and is capable of deeply embedded protocol processing for I/O control, storage, networking, AI and AR/VR.

Highlights of AndesCore N22:

• AndeStar V5 (RV32IMAC) / V5e (RV32EMAC) Instruction Set Architecture (ISA), compliant to RISC-V technology plus Andes extensions architectured for performance and functionality enhancements
• 32-bit, 2-stage pipeline CPU architecture
• 16/32-bit mixable instruction format for compacting code density
• Branch prediction to speed up control code
• Configurable Multiplier
• Physical Memory Protection (PMP)
• Core-Local Interrupt Controller (CLIC) with selective vectoring and priority preemption
• Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting SoC with multiple processors
• Advanced CoDense technology to reduce program code size
• StackSafe hardware to help measuring stack size, and detecting runtime overflow/underflow
• PowerBrake to digitally adjust power (via stalling pipeline)
• Several configurations to tradeoff between core size and performance requirements

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